A processor pipeline is composed of many stages where each stage performs a specific function related to an instruction. Each stage is referred to as a pipe stage or pipe segment. The stages are connected together to form the pipeline. Instructions enter at one end of the pipeline and exit at the other end. The instructions flow sequentially in a stream through the pipeline stages. The stages are arranged so that several stages can be simultaneously processing several instructions. Simultaneously processing multiple instructions at different pipeline stages allows the processor to process instructions faster than processing one instruction at a time, thus improving the execution speed of the processor.
Within the processor, there may be multiple pipelines processing instructions. The individual pipelines may perform unique processor functions. For example, a processor may have one pipeline for executing integer instructions and another pipeline for executing floating point or vector instructions. By separating the pipelines based on functionality of the instruction, the processor may more efficiently utilize its resources when executing the instructions.
Some exemplary instructions that may be processed in the individual pipelines may be conditional instructions. As those skilled in the art appreciate, conditional instructions are instructions which will either execute or not execute if a condition is met or not met. In order to execute a conditional instruction, a condition code register is used to save the most recent condition code value which may be used in the processing of subsequent conditional instructions. The conditional instructions may be executed in any of the pipelines within the processor.
Commonly, in previous ARM (Advanced RISC Machine) processors, there was only one accessible or readable condition code register containing condition code values used to support multiple pipelines. This condition code register was physically located with only one pipeline but coupled to other pipelines. Having only one read accessible condition code register impacted the processor's execution especially when executing conditional instructions in the other remotely located pipelines. The efficiency impact is illustrated when conditional instructions are executed in pipelines having no local condition code register. The condition code value saved in the condition code register is sent to the requesting conditional instruction in the pipeline having no local condition code register when the conditional instruction attempts to execute. However, the condition code value may be updating from a previous instruction when the conditional instruction requests the condition code value. While the new condition code value is being written into the condition code register, the requesting conditional instruction may stall until the new condition code value is available. After the update of the condition code register is completed the new condition code value is read and sent back to the requesting conditional instruction in the pipeline having no local condition code register. As a result, the condition code value retrieval process in pipelines having no local condition code registers may take several processor cycles to complete. The delay in receiving the condition code value may be compounded if an instruction changing the condition code value is executed in the pipeline having no local condition code register and a subsequent conditional instruction executes in the same pipeline. In this instance, the subsequent conditional instruction may have to wait for the new conditional code value to update before it can be read and sent back to that pipeline.